Driving the last inbound signal on a line in a bus with a termination

ABSTRACT

Supporting termination on a bus. According to one embodiment of the present invention a device coupled to a line in the bus receives data from the line. The device stores the data in a storage medium and then drives the data back on the line immediately after receiving the data.

CROSS-REFERENCE TO RELATED APPLICATIONS(S)

[0001] This application is a continuation of U.S. Patent applicationSer. No. 09/219,130, filed on Dec. 22, 1998, the specification of whichis incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The invention relates generally to buses for processor basedsystems, and more particularly to supporting termination on a bus.

BACKGROUND

[0003] Computer systems include a processor, one or more memory devices,and one or more input-output or I/O devices. The processor, the memorydevices, and the I/O devices communicate with each other through a busin the computer system. A bus is a communication link comprising a setof wires or lines connected between the devices listed above. The bus isshared by the devices as they communicate with one another. A bus mayalso be a set of lines connected between two functional circuits in asingle integrated circuit. The bus generally contains a set of controllines and a set of data lines. The control lines carry signalsrepresenting requests and acknowledgments and signals to indicate whattype of data is on the data lines. The data lines carry data, complexcommands, or addresses. A separate set of lines in the bus may bereserved to carry addresses, and these are called address lines. Thedevices communicate with each other over the bus according to a protocolthat governs which devices may use the bus at any one time. The protocolis a set of rules governing communication over the bus that areimplemented and enforced by a device that is appointed a bus master.Generally the processor is the bus master, although there may be morethan one bus master. Each bus master initiates and controls requests touse the bus.

[0004] Two different schemes exist for organizing communication on abus. A synchronous bus includes a clock pulse in the control lines andis governed by a protocol based on the clock pulse. An asynchronous busdoes not rely on a clock pulse to organize communication. Rather, theasynchronous bus is coordinated by a handshaking protocol under which asender communicates directly with a receiver to transfer data based on aseries of mutual agreements. The sender and the receiver exchange a setof handshaking signals over the control lines before, during, and aftereach data transfer.

[0005] Signals are exchanged between the sender and the receiver overthe bus in the following manner. The sender includes a separate drivercircuit, typically including a tri-state output buffer, connected toeach bus line it is to send signals to. Likewise, the receiver has aseparate receiver circuit connected to each bus line it is to receivesignals from. Typically the receiver circuit is a high impedance inputbuffer circuit such as an inverter. When the sender sends a signal on aparticular line it directs the appropriate driver circuit to bring theline to a suitable voltage, either high or low. The receiver detects thesignal in the appropriate receiver circuit to complete thecommunication. A reflection of the signal can take place if the inputimpedance of the receiver circuit is different from the characteristicimpedance of the line. The discontinuity in the impedance causes thereflection. The signal is reflected back and forth along the line andthe reflections must dissipate before a new signal can be sent on theline. This slows the operation of the bus and the computer system.

[0006] Signal reflection also causes inter-symbol interference noise(ISI) on the bus. ISI contributes to timing delay variation which limitsthe frequency at which a bus can transfer signals. It is thereforeadvantageous to reduce ISI in high frequency bus structures.

[0007] A conventional method of reducing reflection on a bus line is todamp or dissipate the reflections with a termination connected to theline. A termination is a dissipating or damping load, typically aresistive device, which has an impedance that is substantially similarto the characteristic impedance of the line. Two types of terminationare used. A source termination comprises an impedance placed in a drivercircuit connected to the bus line. A parallel termination comprisesimpedances placed in a driver circuit and a receiver circuit so thatimpedances are placed at both ends of a bus line. While theimplementation of termination on a bus has been successful in reducingsignal reflection, the implementation itself may cause problems with theoperation and performance of the bus.

[0008] There remains a need for termination in high frequency busstructures and ways of supporting the termination to reduce theabove-mentioned problems. For these and other reasons there is a needfor the present invention.

SUMMARY OF THE INVENTION

[0009] According to one embodiment of the present invention, data isreceived from a line, the data is stored in a storage medium, and thedata is driven back on the line immediately after the data is received.Advantages of the invention will be apparent to one skilled in the artupon an examination of the detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 is an electrical schematic diagram of a receiver circuitaccording to an embodiment of the present invention.

[0011]FIG. 2 is an electrical schematic diagram of an inverter accordingto an embodiment of the present invention.

[0012]FIG. 3 is a block diagram of a system according to an embodimentof the present invention.

[0013]FIG. 4 is an electrical schematic diagram of a matching pair ofdriver/receiver circuits according to an embodiment of the presentinvention.

[0014] FIGS. 5A-5D are timing diagrams each having a strobe signal and acompanion address signal according to alternative embodiments of thepresent invention.

[0015]FIG. 6 is a flowchart of a method according to an embodiment ofthe present invention.

[0016]FIG. 7 is a block diagram of a computer system according to anembodiment of the present invention.

[0017]FIG. 8 is a block diagram of a personal computer according to anembodiment of the present invention.

DETAILED DESCRIPTION

[0018] In the following detailed description of exemplary embodiments ofthe present invention, reference is made to the accompanying drawingswhich form a part hereof, and in which are shown by way of illustrationspecific exemplary embodiments in which the present invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the present invention, andit is to be understood that other embodiments may be utilized and thatlogical, mechanical, electrical and other changes may be made withoutdeparting from the spirit or scope of the present invention. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the claims.

[0019] In this description transistors are described as being in anactive state or switched on when they are rendered conductive by anappropriate control signal, and the transistors are described as beingin an inactive state or switched off when they are renderednon-conductive by the control signal.

[0020] One problem with the implementation of termination is that thereis a substantial dissipation of power by receiver circuits connected toa bus when the bus lines are not being driven and are left floating.This problem is described with reference to a receiver circuit 100 witha center-tapped termination circuit (CTT) shown in FIG. 1 according toan embodiment of the present invention. The receiver circuit 100includes a high impedance input buffer circuit such as an inverter 102for relaying a signal from a terminal 104 on a line in a bus to furthercircuitry. The CTT includes a first impedance device 106 connectedbetween a ground and the terminal 104, and a second impedance device 108connected between the terminal 104 and a supply voltage Vcc. Both thedevices 106, 108 are coupled to a line 110 to receive an enable signalENABLE that switches the devices 106, 108 on or off. When the devices106, 108 are switched off by the ENABLE signal they are not conductiveand the terminal 104 is separated from the voltage Vcc and from groundby open circuits. When the devices 106, 108 are switched on by theENABLE signal they each have the same impedance and couple the terminal104 midway between the voltage Vcc and ground. The devices 106, 108 areswitched on by the ENABLE signal to enable the CTT when the receivercircuit 100 is monitoring the line to receive a signal. The enabled CTTsubstantially reduces signal reflection in the line and therebysubstantially reduces ISI. The devices 106, 108 may include resistorsand transistors of different types. For example, the devices 106, 108could be comprised of N-channel transistors, P-channel transistors, BJTor JFET transistors, or a combination of one or more of the abovelistedtransistors, or a combination of resistors and one or more of theabove-listed transistors.

[0021] In a bus according to an embodiment of the invention there areseveral receiver circuits 100 with an enabled CTT connected to andmonitoring each line in the bus for signals sent from drivers thatarrive unexpectedly. When a line is not being driven high or low by adriver it floats at a voltage Vcc/2 due to the enabled CTT's such as theCTT described above including the devices 106, 108. When the line isallowed to float at the voltage Vcc/2 the inverter 102 in each receivercircuit 100 connected to the line is left in an indeterminate state anddissipates a substantial amount of power. The indeterminate state isdescribed with reference to an electrical schematic diagram of theinverter 102 shown in FIG. 2 according to an embodiment of the presentinvention. The inverter 102 includes an enable transistor 202 having acontrol terminal coupled to the line 110 to receive the ENABLE signal, ahigh-side P-channel transistor 204, and a low-side N-channel transistor206. The transistors 202, 204, 206 are connected between the voltage Vccand ground. Control terminals of the transistors 204, 206 are connectedtogether to the terminal 104 to receive a signal on the line. When theinverter 102 is enabled by the ENABLE signal and the signal at theterminal 104 is either high or low, one of the transistors 204, 206 isswitched on and the other is switched off to invert the signal. However,if the line is floating at the voltage Vcc/2 both of the transistors204, 206 are rendered conductive such that current, called crowbarcurrent, flows through the enabled transistor 202 and the transistors204, 206 to dissipate power. At least some embodiments of the presentinvention described herein address this problem. The present inventionalso provides solutions to other problems not mentioned herein.

[0022] The present invention is described in the context of two devicescommunicating with each other over a bus system. A block diagram of asystem 300 according to an embodiment of the present invention is shownin FIG. 3. The system 300 includes a processor 302 and a cache memory304 connected together by a bus 306. The bus 306 includes a strobe line310 and a set of address lines 312. The processor includes controlcircuitry 320 connected to a register 322 for controlling a set ofcombined driver/receiver circuits 324, each driver/receiver circuit 324being connected to one of the lines 310, 312 in the bus 306. Eachdriver/receiver circuit 324 is connected to a set of lines 326 toexchange signals with the control circuitry 320. The cache memory 304also includes control circuitry 330 connected to a register 332 forcontrolling a set of combined driver/receiver circuits 334, eachdriver/receiver circuit 334 being connected to one of the lines 310, 312in the bus 306. Each driver/receiver circuit 334 is connected to a setof lines 336 to exchange signals with the control circuitry 330.

[0023] An electrical schematic diagram of a matching pair ofdriver/receiver circuits 324, 334 connected to communicate over one ofthe lines 312 according to an embodiment of the present invention areshown in FIG. 4. The elements in the driver/receiver circuits 324, 334are similar and operate in a similar manner, and therefore only thedevices in the driver/receiver circuit 334 are described with referencecharacters for purposes of brevity. The driver/receiver circuit 334includes a high-impedance receiver 410 such as an inverter for receivingand relaying a signal from the line 312 to the control circuitry 330 onone of the lines 336. The driver/receiver circuit 334 includes a CTTwith a first impedance device 412 connected between a ground and theline 312, and a second impedance device 414 connected between the line312 and a supply voltage Vcc. A driver 416 is connected to drive theline 312 with a signal provided by the control circuitry 330 on one ofthe lines 336. The receiver 410, the CTT, and the driver 416 are coupledto one of the lines 336 to receive an enable signal ENABLE that enablesor disables the driver 416 and is inverted by an inverter 418 to enableor disable the CTT and the receiver 410. At the appropriate time thecontrol circuitry 330 provides the ENABLE signal to enable the driver416 and disable the CTT and the receiver 410 to drive a signal on to theline 312. When the driver/receiver circuit 334 is about to receive asignal from the line 312 the control circuitry 330 changes the ENABLEsignal to disable the driver 416 and enable the CTT and the receiver410, and the receiver 410 relays the signal to the control circuitry 330while the enabled CTT substantially reduces signal reflection on theline 312.

[0024] The processor 302 and the cache memory 304 are controlled bytheir respective control circuitry 320, 330 to exchange addresses overthe address lines 312 under a protocol according to an embodiment of thepresent invention. For purposes of brevity the protocol is describedwith respect to a single address line 312 and the strobe line 310,although one skilled in the art having the benefit of this descriptionwill understand that the protocol is applicable to one or more of theaddress lines 312 and, in alternative embodiments of the invention, toone or more of a group of data lines and a group of control lines in thebus 306. The processor 302 is appointed the bus master under theprotocol. The processor 302 drives address signals on to the bus 306when no other device is driving address signals on to the bus 306. Theprocessor 302 enables its driver and disables its CTT and receiver todrive a signal, high or low, on the line 312. The cache memory 304disables its driver and enables its CTT and receiver to monitor the line312 for the signal from the processor 302 that may arrive unexpectedly.The processor 302 may send a series of signals on the line 312. Thecache memory 304 captures the signals with a strobe signal and storesthe last inbound signal in the register 332. One skilled in the arthaving the benefit of this description will recognize that the lastinbound signal may be stored in any other storage medium such as amemory, or in a dedicated circuit such as a sequential circuit such as aflip-flop circuit with an asynchronous set and reset. The processor 302then requests an address from the cache memory 304 and disables itsdriver while enabling its CTT and receiver to prepare to receive theaddress. The cache memory 304, in response to the request, disables itsCTT and receiver and enables its driver, and immediately begins drivingthe last inbound signal stored in the register 332 back on to the line312. This is done to substantially reduce the possibility of buscontention if the processor 302 has not yet disabled its driver. Inother words, the processor 302 may still be driving the last signal whenthe cache memory 304 has enabled its driver, and if the cache memory 304starts by driving the new address there may be contention on the line312. Under the protocol the cache memory 304 drives the last inboundsignal on to the line 312 for a few clock cycles, and then drives astrobe signal, a square wave signal, on the strobe line 310, and a newaddress signal on the line 312 such that the processor 302 latches thenew address signal on a leading edge of the strobe signal. A timingdiagram of the strobe signal is shown in FIG. 5A with a leading edgecoincident with the new address signal. The processor 302 enables itsCTT and receiver in time to receive the new address signal because ithas knowledge of the protocol and therefore knows when the strobe signalis going to arrive. The cache memory 304 drives an address signal ontothe line 312 and thereafter disables its driver and enables its CTT andreceiver. The processor 302 stores the new address signal in theregister 322 and then disables its CTT and receiver, enables its driver,and immediately begins to drive the new address signal back on to theline 312 to substantially reduce the possibility of bus contention whilethe cache memory 304 is disabling its driver. In this way the protocolprovides for bus master overlaps so that two drivers are driving theline 312 at the same time when one of the drivers is being disabled andthe other is being enabled. The line is driven at a voltage, either highor low, to substantially reduce crowbar current and power dissipation.The two drivers drive the line 312 with the same signal to substantiallyreduce the possibility of bus contention.

[0025] Alternative protocols according to embodiments of the presentinvention are described with reference to FIGS. 5B-5D, each of whichshow a timing diagram of a strobe signal and a companion address signal.With reference first to FIG. 5B, a protocol may be designed such thatafter being requested to send an address to the processor 302 the cachememory 304 sends a strobe signal with two pulses to the processor 302.In response the processor 302 disables its driver on the rising edge ofthe first pulse, enables its CTT and receiver on the trailing edge ofthe first pulse, and latches the address signal on a rising edge of thesecond pulse. The processor 302 may then immediately drive the addresssignal back on to the line 312. An alternate protocol may be designedsuch that the cache memory 304 sends a strobe signal with a single pulseto the processor 302, and the processor 302 disables its driver andenables its CTT and receiver on the rising edge of the pulse and latchesthe new address signal on the falling edge of the pulse. The processor302 may then immediately drive the new address signal back on to theline 312. A timing diagram of a strobe signal and an address signal areshown in FIG. 5C according to this protocol. Another protocol may bedesigned with active-low logic according to a timing diagram of a strobesignal and an address signal shown in FIG. 5D. One skilled in the arthaving the benefit of this description will recognize that a protocolmay be designed according to an embodiment of the present invention inwhich the above listed events take place on any combination of selectededges of a strobe signal.

[0026] A flowchart of a method 600 for transferring data between a firstdevice and a second device over a bus according to an embodiment of thepresent invention is shown in FIG. 6. In 602 a driver is enabled and aCTT and a receiver are disabled in the first device. Also, a CTT and areceiver are enabled and a driver is disabled in a second device. In 604the first device drives data on to the bus. In 606 the last inbound datafrom the bus is received and stored in the second device. In 608 the CTTand the receiver of the second device are disabled and the driver in thesecond device is enabled. Also, the driver of the first device isdisabled and the CTT and the receiver are enabled in the first device.In 610 the last inbound data that was stored in 606 is driven back on tothe bus from the second device. The second device then drives new dataon to the bus in 612. In 614 the last inbound new data is received andstored by the first device. In 616 the driver is enabled and the CTT andthe receiver are disabled in the first device, and the CTT and thereceiver are enabled and the driver is disabled in the second device. In618 the last inbound new data that was stored in 614 is driven back onto the bus from the first device, and the method ends. Those skilled inthe art having the benefit of this description will understand that tocontinue the communication between the first and second devices themethod returns to 602. According to the method 600, each time data isdriven on to the bus the data may be driven in a sequence of more thanone bit of data. If this occurs, then the last bit driven on to the busis stored as the last inbound data by the receiving device. The method600 provides for driving data on to the bus to substantially reduce thetime the bus is floating, and to substantially reduce the possibility ofbus contention by controlling each device to start driving the lastinbound data back on to the bus. One skilled in the art having thebenefit of this description will understand that the steps of the method600 may be repeated to provide for communication between more than twodevices over the bus.

[0027] One skilled in the art having the benefit of this descriptionwill understand that the method 600 may be carried out for each line ina bus between the first and second devices, and for additional devicesconnected to the bus. The method 600 may be modified according to any ofthe embodiments of the invention described above, and may be implementedin many different ways. For example, the method 600 may be implementedincluding strobe signals sent concurrently with the data according tothe strobe signals shown in FIGS. 5A-5D. The method 600 may beimplemented for data lines, address lines, control lines, or anycombination thereof. The method 600 may also be implemented as a seriesof programmable instructions stored and implemented in the respectivecontrol circuitry 320, 330 of the processor 302 and the cache memory304. All of the embodiments of the present invention described,including the method 600, may be implemented with alternative types ofcircuitry or hardware including one or more of the following: hardwiredlogic, a Field Programmable Gate Array (FPGA), a hardwired FPGA,programmable logic, a programmable microcontroller, an ApplicationSpecific Integrated Circuit (ASIC), a Read Only Memory (ROM), or asequencer, or any suitable combination thereof.

[0028] The embodiments of the invention described above may beimplemented in a computer system such as a computer system 700 accordingto an embodiment of the present invention and shown in a block diagramin FIG. 7. The computer system 700 includes a processor 702, two memorydevices 704, 706, and two input/output (I/O) devices 708, 710. Each ofthe memory devices 704, 706 is either a randomaccess memory (RAM), aread-only memory (ROM), a cache memory, or a storage device such as ahard disk drive, a floppy disk drive, an optical disk drive, or a tapecartridge drive. Each of the I/O devices 708, 710 is either a monitor, apointing device such as a mouse, a keyboard, or a modem. The devices inthe computer system 700 including the processor 702, the two memorydevices 704, 706, and the two I/O devices 708, 710 communicate with eachother through a bus 712 connected to the devices. Signals are sent onthe bus 712 as needed by one or more of the devices, and arrive at otherdevices under a protocol according to one of the embodiments of thepresent invention described above. Each of the devices connected to thebus has a CTT, a receiver, and a driver for each line in the bus thatare controlled by control circuitry as described above. Data may bedriven on to the bus to substantially reduce the time the bus isfloating and each device may begin driving the last inbound data tosubstantially reduce the possibility of bus contention. One skilled inthe art having the benefit of this description will recognize that moredevices such as processors, memory circuits, and I/O devices may beconnected to the bus 712.

[0029] Those skilled in the art having the benefit of this descriptioncan appreciate that the present invention may be practiced with anycomputerized system including a bus. Such computerized systems mayinclude, for example, a video game, a handheld calculator, a personalcomputer, or a multi-processor supercomputer, or an informationappliance such as, for example, a cellular telephone, a pager, or adaily planner or organizer, or an information component such as, forexample, a magnetic disk drive or telecommunications modem, or otherappliance such as, for example, a hearing aid, washing machine ormicrowave oven having an electronic controller.

[0030] The computer system 700 shown in FIG. 7 may take the form of apersonal computer 800 shown in FIG. 8. The personal computer 800includes a computer 810 that is operatively coupled to a monitor 812, apointing device 814, and a keyboard 816. The computer 810 includes aprocessor, a random-access memory (RAM), a read-only memory (ROM), andone or more storage devices, such as a hard disk drive, a floppy diskdrive (into which a floppy disk can be inserted), an optical disk drive,and a tape cartridge drive. The memory, hard drives, floppy disks, etc.,are types of computer-readable media. The present invention is notparticularly limited to one type of computer 810. The monitor 812permits the display of information within a viewing area, includingcomputer, video and other information, for viewing by a user of thepersonal computer 800. The present invention is not limited to anyparticular monitor 812, and the monitor 812 is one type of displaydevice that may be used in a system with the present invention. Suchmonitors include cathode ray tube (CRT) displays, as well as flat paneldisplays such as liquid crystal displays (LCD's). The pointing device814 permits a control of the screen pointer provided by graphical userinterfaces. The present invention is not limited to any particularpointing device 814. Such pointing devices include mouses, touch pads,trackballs, wheels, remote controls and point sticks. Finally, thekeyboard 816 permits entry of textual information into the computer 810,as known within the art having the benefit of this description, and thepresent invention is not limited to any particular type of keyboard.

[0031] Although specific embodiments have been illustrated and describedherein, it will be appreciated by those skilled in the art having thebenefit of this description that any equivalent arrangement may besubstituted for the specific embodiments shown. For example, theembodiments of the invention may be applied to data lines, controllines, or address lines in a bus, or any combination thereof. Thepresent invention is therefore limited only by the claims andequivalents thereof.

What is claimed is:
 1. A method comprising: receiving data from a line;storing the data in a storage medium; and driving the data back on theline immediately after receiving the data.
 2. The method of claim 1,further comprising driving new data on the line after driving the databack on the line.
 3. The method of claim 2, further comprising: enablinga termination circuit and a receiver coupled to the line beforereceiving the data; disabling the termination circuit and the receiverafter receiving the data; and enabling a driver to drive the data backon the line immediately after receiving the data.
 4. The method of claim3 wherein: enabling a termination circuit comprises enabling a pluralityof center-tapped termination circuits and a plurality of receivers for aplurality of address lines in a bus, each receiver comprising a buffer;receiving data comprises receiving a plurality of inbound addresses fromthe address lines; storing the data comprises storing a last inboundaddress in a register as a stored address; disabling the terminationcircuit comprises disabling the termination circuits and the receivers;enabling a driver comprises enabling a plurality of drivers for theaddress lines in the bus; driving the data comprises driving the storedaddress back on the address lines; and driving new data comprisesdriving a new address on the address lines.
 5. A method for operating asystem comprising: receiving first data from a line in a first circuit;storing the first data in a storage medium in the first circuit; drivingthe first data back on the line from the first circuit immediately afterreceiving the first data; and driving second data on the line from thefirst circuit to a second circuit after driving the first data back onthe line.
 6. The method of claim 5, further comprising: disabling atermination circuit and a receiver in the first circuit and enabling adriver in the first circuit before driving the first data back on theline; and disabling a driver and enabling a termination circuit and areceiver in the second circuit before driving the second data on theline.
 7. The method of claim 6, further comprising: receiving the seconddata from the line in the second circuit; storing the second data in astorage medium in the second circuit; disabling the termination circuitand the receiver in the second circuit and enabling the driver in thesecond circuit; driving the second data back on the line from the secondcircuit immediately after receiving the second data; and disabling thedriver and enabling the termination circuit and the receiver in thefirst circuit.
 8. The method of claim 7 wherein: receiving first datacomprises: disabling the driver and enabling the termination circuit andthe receiver in the first circuit; and receiving a plurality of inboundfirst data signals from a plurality of data lines in a bus; storing thefirst data comprises storing last inbound first data signals for eachdata line in a register in the first circuit; driving the first databack on the line comprises driving the last inbound first data signalsback on to each data line; driving second data on the line comprises:driving a strobe signal on a strobe line from the first circuit to thesecond circuit; and driving a plurality of second data signals on toeach data line from the first circuit to the second circuit; receivingthe data in the second circuit comprises latching the second datasignals in the second circuit on an edge of the strobe signal; storingthe second data comprises storing last inbound second data signals foreach data line in a register in the second circuit.
 9. The method ofclaim 8 wherein: receiving a plurality of inbound first data signalscomprises receiving a plurality of inbound first address signals from aplurality of address lines in a bus; driving a strobe signal comprisesdriving a strobe signal on the strobe line having a plurality of edgesfrom a cache memory to a processor; and disabling a driver and enablinga termination circuit and a receiver in the second circuit comprisesdisabling the driver and enabling the termination circuit and thereceiver in the processor on an edge of the strobe signal beforelatching the second data signals in the processor.
 10. The method ofclaim 7 wherein: receiving first data comprises: receiving a firststrobe signal on a first strobe line in the first circuit; disabling thedriver and enabling the termination circuit and the receiver in thefirst circuit on a first edge of the first strobe signal; and latching aplurality of inbound first data signals from a plurality of data linesin a bus in the first circuit on a second edge of the first strobesignal following the first edge of the first strobe signal; storing thefirst data comprises storing last inbound first data signals for eachdata line in a register in the first circuit; driving the first databack on the line comprises driving the last inbound first data signalsback on to each data line; driving second data on the line comprises:driving a second strobe signal on a second strobe line from the firstcircuit to the second circuit; and driving a plurality of second datasignals on to each data line from the first circuit to the secondcircuit; disabling a driver and enabling a termination circuit and areceiver in the second circuit comprises disabling a driver and enablinga termination circuit and a receiver in the second circuit on a firstedge of the second strobe signal; receiving the second data compriseslatching the second data signals in the second circuit on a second edgeof the second strobe signal following the first edge of the secondstrobe signal; storing the second data comprises storing last inboundsecond data signals for each data line in a register in the secondcircuit.
 11. A circuit comprising: a termination circuit coupled to aline; a receiver coupled to the line to receive data from the line; astorage medium to store the data; a driver coupled to the line; and acontrol circuit to: enable the termination circuit and the receiver toreceive the data; store the data in the storage medium; disable thetermination circuit and the receiver; enable the driver; and cause thedriver to drive the data back on the line immediately after the data hasbeen received.
 12. The circuit of claim 11 wherein the control circuitcomprises elements or instructions to: store last inbound data that isreceived from the line in the storage medium; disable the terminationcircuit and the receiver; enable the driver; cause the driver to drivethe last inbound data back on the line immediately after the lastinbound data is received; and cause the driver to drive new data on theline after the last inbound data has been driven back on the line. 13.The circuit of claim 11 wherein the line comprises a plurality ofaddress lines in a bus.
 14. The circuit of claim 11 wherein thetermination circuit comprises a center-tapped termination circuitcoupled to the line and comprising a first impedance device coupledbetween a supply voltage and the line and a second impedance coupledbetween a reference voltage and the line, the first and secondimpedances being switched on when the termination circuit is enabled bythe control circuit and being switched off when the termination circuitis disabled by the control circuit.
 15. The circuit of claim 11 wherein:the receiver comprises a buffer circuit coupled to an address line andis enabled by the control circuit; the driver is enabled by the controlcircuit; the storage medium comprises a register; and the terminationcircuit, the receiver, the storage medium, the driver, and the controlcircuit are included in a cache memory or a processor.
 16. A systemcomprising: a first circuit coupled to a line to receive and store firstdata from the line, to drive the first data back on to the lineimmediately after receiving the first data, and then to drive seconddata on to the line; and a second circuit coupled to the line to receiveand store the second data from the line, and to drive the second databack on to the line immediately after receiving the second data.
 17. Thesystem of claim 16 wherein the second circuit is coupled to the line todrive third data on to the line after driving the second data back on tothe line.
 18. The system of claim 16 wherein each of the first andsecond circuits comprise: a termination circuit coupled to the line; areceiver coupled to the line; a storage medium; a driver coupled to theline; and a control circuit.
 19. The system of claim 18 wherein thecontrol circuit of the first circuit comprises elements or instructionsto: enable the termination circuit and the receiver of the first circuitto receive the first data from the line; store the first data in thestorage medium of the first circuit; disable the termination circuit andthe receiver and to enable the driver of the first circuit; cause thedriver of the first circuit to drive the first data back on the lineimmediately after the first data has been received; and drive seconddata on the line after driving the first data back on the line.
 20. Thesystem of claim 19 wherein: store the first data comprises store thelast inbound first data in the storage medium of the first circuit; andcause the driver of the first circuit comprises cause the driver of thefirst circuit to drive the last inbound first data back on the lineimmediately after the first data has been received.
 21. The system ofclaim 19 wherein the control circuit of the second circuit compriseselements or instructions to: enable the termination circuit and thereceiver of the second circuit to receive the second data; store thesecond data in the storage medium of the second circuit; disable thetermination circuit and the receiver and to enable the driver of thesecond circuit; and cause the driver of the second circuit to drive thesecond data back on the line immediately after the second data has beenreceived.
 22. The system of claim 21 wherein: store the second datacomprises store the last inbound second data in the storage medium ofthe second circuit; and cause the driver of the second circuit comprisescause the driver of the second circuit to drive the last inbound seconddata back on the line immediately after the second data has beenreceived.
 23. The system of claim 21 wherein: the line comprises aplurality of lines and a strobe line in a bus; each of the first andsecond circuits comprise a driver coupled to the strobe line; thecontrol circuit of the first circuit comprises elements or instructionsto drive a first strobe signal on the strobe line having a plurality ofedges; and the control circuit in the second circuit comprises elementsor instructions to: enable the termination circuit and the receiver ofthe second circuit on an edge of the first strobe signal; latch thesecond data on an edge of the first strobe signal; and drive a secondstrobe signal on the strobe line having a plurality of edges.
 24. Thesystem of claim 23 wherein the control circuit of the second circuitcomprises elements or instructions to cause the driver of the secondcircuit to drive third data on to the line; the control circuit of thefirst circuit comprises elements or instructions to: enable thetermination circuit and the receiver of the first circuit on an edge ofthe second strobe signal; and latch the third data on an edge of thesecond strobe signal.
 25. The system of claim 23 wherein the controlcircuit of the second circuit comprises elements or instructions tocause the driver of the second circuit to drive third data on to theline; the control circuit of the first circuit comprises elements orinstructions to: enable the termination circuit and the receiver of thefirst circuit on a first edge of the second strobe signal; and latch thethird data on a second edge of the second strobe signal following thefirst edge.
 26. The system of claim 23 wherein: the lines comprise aplurality of address lines and a strobe line in the bus; and the first,second, and third data comprise a first, second, and third addresses,respectively.
 27. The system of claim 23 wherein the terminationcircuits in the first and second circuits each comprise a center-tappedtermination circuit.
 28. The system of claim 23 wherein: the receiversin each of the first and second circuits comprise a buffer circuit; thestorage mediums in each of the first and second circuits comprise aregister; the first circuit comprises a cache memory; and the secondcircuit comprises a processor.